1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to an output circuit of a semiconductor memory device and a method of outputting data in a semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices are generally used for data storage and retrieval. Random-access memory (RAM) is a type of a volatile memory, and is primarily used as a main memory of a computer. Dynamic RAM (DRAM) is a type of RAM, and includes memory cells. Each of the memory cells includes a cell transistor and a cell capacitor, and store data in the form of electric charge in the cell capacitor which is translated to binary “0” and “1”.
Each of the memory cells of the DRAM is coupled to a word line and a bit line. When the cell transistor is turned on in response to a word line enable signal, the data stored in the cell capacitor are output to the bit line, or the data of the bit line are stored in the cell capacitor.
FIG. 1 is a block diagram illustrating a structure of a conventional semiconductor memory device, for example, of the type disclosed in Korean Patent Laid-Open Publication No. 2000-8508.
Referring to FIG. 1, the semiconductor memory device includes a plurality of memory cells 10a, 10b, . . . , 10n, a plurality of precharging and equalizing circuits 20a, 20b, . . . , 20n, a row address decoder 40, a plurality of column selection switches 30a, 30b, . . . , 30n, a column address decoder 50, a sense amplifier 60 and an output circuit 70.
The row address decoder 40 decodes a row address X to generate a plurality of word line selection signals WL1, WL2, . . . , WLn. In response to the word line selection signals WL1, WL2, . . . , WLn, the memory cells 10a, 10b, . . . , 10n are selected. The precharging and equalizing circuits 20a, 20b, . . . , 20n precharge and equalize a plurality of pairs of bit lines BL1 and BLB1, BL2 and BLB2, . . . , BLn and BLBn during a read operation. The column address decoder 50 decodes a column address Y to generate a plurality of column selection signals Y1, Y2, . . . , Yn. Each of the column selection switches 30a, 30b, . . . , 30n transfers data, which is received from the pair of bit lines that is selected in response to each of the column selection signals Y1, Y2, . . . , Yn, to a corresponding pair of data lines DLk and DLBk. When the sense amplifier 60 is enabled during the read operation, the sense amplifier 60 senses a voltage difference between data transferred from the pair of data lines DL and DLB to amplify the voltage difference between the data, and generates a sense output signal SAS. The output circuit 70 buffers the sense output signal SAS to generate output data DQ.
As the operating speed of semiconductor memory devices is increased, the output circuit requires a predetermined delay time interval for outputting data. A time interval tAA corresponding to a period from a time at which a read command is input, to a time at which corresponding data is output from the output circuit 70 can be varied depending on a manufacturing process. Conventional semiconductor memory devices commonly employ a column address strobe (CAS) latency 4 (CL4) pipeline mode or a CAS latency 3 (CL3) pipeline mode. The CL4 pipeline mode further includes a switching operation, unlike the CL3 pipeline mode. The CL3 pipeline mode outputs corresponding data when three clock cycles elapse after the read command is input. The CL4 pipeline mode outputs corresponding data when four clock cycles elapse after the read command is input. For example, when the time interval tAA is about 30 ns and one clock cycle is about 10 ns, the CL3 pipeline mode has to output corresponding data within about 30 ns of elapsed time after the read command is input. Accordingly, an operating margin of the CL3 pipeline mode is insufficient. However, the CL4 pipeline mode outputs corresponding data within about 40 ns of elapsed time after the read command is input; thus, because the time interval tAA is about 30 ns, an operating margin of the CL4 pipeline mode is about 10 ns. As a result, when the CL4 pipeline mode is employed instead of the CL3 pipeline mode, limitations of the time interval tAA can be relieved.
When the operating speed of a semiconductor memory device is increased, there can be a phase inversion between switch control signals for controlling the output circuit of the semiconductor memory device. For example, when a phase of one switch control signal lags behind that of an external clock signal and a phase of another switch control signal leads that of the external clock signal, a phase inversion can occur between the two switch control signals as the frequency of the external clock signal becomes higher. That is, because a phase inversion phenomenon can occur between the switch control signals even in the conventional CL4 pipeline mode, an operating frequency of the semiconductor memory device is thereby limited.